We have now reached a point where microelectronics can no longer keep pace with the increased requirements of communication systems, especially with respect to energy efficiency for wireless transceivers, which have tightly constrained power and energy budgets. Thus, the complexity of implementing advanced FEC schemes to operate at Tb/s data rates is critical.
Advanced channel coding schemes are necessary to achieve outstanding communications performance, of which Turbo-, LDPC-, and Polar Codes are the most promising. However, these solutions come with considerable implementation challenges, especially when targeting stringent power constraints. The EPIC project addressed these challenges and developed implementation-ready FEC technology for these code families, which meet the cost and performance requirements of future wireless Tb/s use-cases.
EPIC methodology differentiates itself by combining code construction, decoding algorithm design and architecture/implementation in a holistic way, allowing for optimization over larger domains. The project designed a thorough and detailed design framework based on EPIC Design Space Exploration (DSE). This novel and disruptive approach has enabled the partners to develop unrivaled codes, encoder and decoder architectures. The consortium has been able to demonstrate world-leading performance by providing order-of-magnitude performance improvements with respect to 5G systems and by delivering next generation FEC classes.
Podcast about the results:
European Commission's Innovation Radar published EPIC results
- Improved turbo code design, simplified decoder algorithms and architectures for very high throughput applications (TB)
- ASIC design for terabit-per-second forward error correction coding scheme based on polar codes (POL)
- Enabling low-latency Tbps communication by introducing a frame level interleaved LDPC decoder (IMEC)
- High throughput forward error correction architectures for next generation communication systems (TUKL)
- Improved Terrabit Decoders for ASIC and FPGA technologies (CRE)
- Multi-dimensional differential-triangle set codes to achieve practical >100Gbps throughput (IDCC)
Creonics presenteds the EPIC Demonstrator at the EuMWEEK conference in Madrid
The Goals of the Project are:
- to design and implement next generation Forward-Error-Correction for wireless Tb/s technology and Beyond-5G systems.
- to advance state-of-the-art codes and develop the principal channel coding technology for wireless Tb/s technology.
- to devise a disruptive FEC design framework to unify algorithmic and implementation domains.
- to validate and demonstrate the developed FEC technology in virtual silicon tape-out and provide first-in-class wireless Tb/s FEC chipset architecture block.
- to put the scientific excellence and contributions to wireless industry in the domain of B5G standardization and technology development at the centre of the project execution.
The project consortium consists of:
- Technikon Forschungs- und Planungsgesellschaft mbH, Villach
- InterDigital Europe Ltd., London
- Interuniversitair Micro- Electronica Centrum (imec), Leuven
- Polaran Ltd., Ankara
- Rheinland-Pfälzische Technische Universität (RPTU), Kaiserslautern / Landau
- Ericsson AB, Stockholm
- Institut Mines-Télécom, IMT Atlantique, Brest
Creonic GmbH, Kaiserslautern