An IP core may contain the following elements: 

• Hardware model as netlist or encrypted source code for AMD Xilinx / Intel / Microchip FPGAs
• Hardware model as VHDL / Verilog source code
• Bit-accurate software reference model as pre-compiled library for Linux or Windows. You can easily integrate this model into your Matlab, C or C++ environment.
• Test environment for the hardware of the IP core consisting of VHDL testbench and test data as well as post-synthesis simulation model or pre-compiled simulation model.
• Delivery will be made by download from a secure server located in Germany.