SDA OCT

Encoder and Decoder

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The Optical Communications Terminal (OCT) Standard was developed by the Space Development Agency (SDA) with the purpose of bringing interoperability across freespace optical communication (FSO) systems where at least one endpoint is a space-based terminal. 

The Creonic SDA OCT Encoder handles the construction of Over-The-Air (OTA) frames as indicated in the standard, a preamble followed by a header and payload data, with both fields being protected by cyclic redundancy check (CRC) and forward error correction (FEC). The Creonic SDA OCT Decoder performs the synchronization of the Over-The-Air (OTA) frame and then decodes the header and payload data within the frame.  

  

FLEXIBILITY

LATENCY

THROUGHPUT

ERROR CORRECTION


Interested? Contact us!​

Kevin Christoffers 
Director - Business Development & Sales


Product Brief

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Applications

  • Free-space optical communications (FSO) systems such as
    • space-to-space (S2S)
    • space-to-air (S2A)
    • space-to-maritime (S2M)
    • space-to-ground (S2G)






  • ​Compliant with "Optical Communications Terminal (OCT) Standard Version 3.0, Document ID: SDA-9100-001-05, August 2021"
  • Compliant with "Optical Communications Terminal (OCT) Standard Version 3.1.0, Document ID: SDA-9100-001-08, March 2024"
  • Compliant with "Optical Communications Terminal (OCT) Standard Version 4.0.0, Document ID: SDA-9100-001-09, August 2024"
  • Support for payload code rates 11/13, 22/29, 2/3, 1/2, and uncoded data

Features

We are ISO 9001:2015 certified

Our customers can rely on consistently high quality, guaranteed by our certified quality management.     

Quality

Benefits

  • Low-power and low-complexity design
  • AXI4-Stream data and configuration interfaces for a seamless integration
  • Collection of statistical information (frame counters, CRC error counters, synchronization loss counters, etc.)
  • Configurable preamble synchronization  
  • Deliverable includes Vivado IP Package, VHDL source code or synthesized netlist, VHDL testbench, and bit-accurate Matlab, C or C++ simulation model  
  • Available for ASIC and FPGAs (AMD / Xilinx, Intel / Altera, Microchip)


Related Links

Creonic MISC FEC and DSP Encoder and Decoder IP cores