The Creonic DVB-S2X Demodulator is a low-complexity high-performance solution that allows for symbol rates of up to 100 MSymb/s on state-of-the-art FPGAs and performs all tasks of an inner receiver. The demodulator expects the quantized, complex baseband samples from an analog-digital-converter (ADC) and recovers timing, frequency and phase of the complex mapped symbols. In addition, the core handles PL frame recovery and PL de-framing. The demodulator’s output perfectly fits the Creonic DVB-S2X forward error correction IP core that implements LDPC and BCH decoding.
DVB-S2X is the next generation satellite
transmission standard which is an extended version of its
well established predecessor DVB-S2. The new specification allows for spectral efficiency gains of up to 50% by offering lower roll-off factors, higher modulations and a finer code rate granularity compared to DVB-S2.
Interested? Contact us!
Kevin Christoffers
Director - Business Development & Sales
Product Brief
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- Satellite communication (Digital Video Broadcasting, Interactive Services, News Gathering, Professional Services)
- Nanosatellite and CubeSat devices
- Compliant with DVB-S2 and DVB-S2X
- Supports ACM, CCM, and VCM modes
- Support for short and long blocks (16,200 bits and 64,800 bits)
- Support for QPSK to 256-APSK
- Support for very low SNR modes (VLSNR) optional
- Output of XFEC FRAMEs for further processing by the Creonic FEC Decoder
We are ISO 9001:2015 certified
Our customers can rely on consistently high quality, guaranteed by our certified quality management.
- Validated against 3rd party DVB-S2X Modulators
- The Demodulator contains radio interface, decimator, timing recovery, equalizer, frame acquisition, and carrier recovery
- Demodulator performs and supports spectrum inversion, DC offset correction, I/Q imbalance correction, decimation, coarse frequency estimation, timing recovery, matched filtering, downsampling, frame synchronization, PL descrambling, fine frequency correction, phase correction, automatic gain control, and PL deframing
- Low-power and low-complexity design
- On-the-fly configuration
- AXI4-Lite interface for controlling the core and retrieving status information
- Very fast synchronization due to different sets of filter coefficients for acquisition and tracking modes
- Configurable interrupts and output of synchronization status information
- Perfectly fits to the Creonic DVB-S2X LDPC/BCH Decoder
- Deliverables include VHDL source code or synthesized netlist, HDL simulation models, VHDL testbench, and bit-accurate Matlab, C or C++ simulation model
- Available for ASICs and FPGAs (Altera / Intel, AMD / Xilinx, Microchip)
