DVB-S2 Demodulator
DVB-S2 (Digital Video Broadcast – Satellite 2nd Generation) is an ETSI
standard of the second generation for digital data transmission via
satellites. It was published in 2005, being the first standard of the
second generation DVB standards (DVB-S2/DVB-T2/DVB-C2). Because of its
capacity-approaching forward error correction, today DVB-S2 is the
de-facto standard in satellite communication and other applications. The
Creonic DVB-S2 high performance demodulator IP core performs all tasks
of an inner receiver. Its output perfectly fits the DVB-S2 forward error
correction IP core from Creonic that implements LDPC and BCH decoding.
Applications
- Satellite communication (Digital Video Broadcasting, Interactive Services, News Gathering, Professional Services)
- Nanosatellite and CubeSat devices
Standard Features the Core Supports
- Compliant with ETSI 302 307 V1.2.1 (2009-08) (DVB-S2)
- Supports CCM mode for broadcasting. ACM and VCM modes will be available soon
- Support for QPSK and 8-PSK modulations. 16-APSK and 32-APSK will be available soon
- Support for short blocks (16200 bits) and long blocks (64800 bits)
- Output of XFECFRAMEs for further processing by the Creonic DVB-S2 FEC decoder IP core
Your Benefits
- The demodulator contains radio interface, decimator, timing recovery, equalizer, frame acquisition, and carrier recovery
- Demodulator performs and supports spectrum inversion, DC offset correction, I/Q imbalance correction, decimation, coarse frequency estimation, timing recovery, matched filtering, downsampling, frame synchronization, PL descrambling, fine frequency correction, phase correction, automatic gain control, and PL deframing
- Low-power and low-complexity design
- Very fast synchronization due to different sets of filter coefficients for acquisition and tracking mode
- Very fast synchronization due to different sets of filter coefficients for acquisition and tracking mode.
- AXI4-Stream handshaking interfaces for seamless integration
- Available for ASIC and FPGAs (AMD Xilinx, Intel)
- Deliverable includes VHDL source code or synthesized netlist, VHDL testbench, and bit-accurate Matlab, C or C++ simulation model
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