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    DVB-RCS 

    Turbo Decoder

    ​

    DVB-RCS (Digital Video Broadcasting – Interaction channel for satellite distribution systems) is an established ETSI standard for digital data transmission via satellites. It uses a 8-state double-binary turbo code that has an excellent error correction performance. This outstanding performance of the DVB-RCS turbo codes makes it the ideal candidate for further applications where high spectral efficiency is key for lowering costs.  

      

    FLEXIBILITY

    LATENCY

    THROUGHPUT

    ERROR CORRECTION


    Interested? Contact us!​

    Kevin Christoffers 
    Director - Business Development & Sales


    Product Brief

    Download for more information.


    Applications

    • ​Compliant with ETSI 301 790 V1.4.1 (2005-09) (DVB-RCS)
    • Support for all DVB-RCS payload block sizes (12 to 216 bytes) and code rates (1/3 to 6/7)
    • Support for QPSK and 8-PSK modulation interfaces

    Features

    • Satellite communication

      • Interactive Services
      • Professional Services
      • TDMA
    • Applications with the highest 
      demands on forward error correction
    • Applications with the need for a wide range of code rates (1/3 and above) and block lengths






    We are ISO 9001:2015 certified

    Our customers can rely on consistently high quality, guaranteed by our certified quality management.     

    Quality

    Benefits

    • Gains up to 4 dB compared to convolutional codes
    • Design-time configuration of throughput, input bit widths, and maximum block length for optimal resource utilization
    • Low-power and low-complexity design
    • Burst-to-burst on-the-fly configuration
    • Configurable interleaver parameters allow for support of custom block lengths
    • On-the-fly bit error rate measurement
    • High block length and code rate granularity
    • Configurable amount of turbo decoder iterations for trading-off throughput and error correction performance
    • Allows for easy migration from legacy DVB-RCS turbo decoders
    • Allows for turbo synchronization to further improve error correction performance (on request)
    • Deliverable includes VHDL source code or synthesized netlist, VHDL testbench, and bit-accurate Matlab, C or C++ simulation model ​
    • Available for ASIC and FPGAs (AMD / Xilinx, Intel / Altera, Microchip)


    Related Links


    DVB-RCS Standard



    Creonic Turbo Decoder IP Cores


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