CCSDS SCCC Turbo 
Encoder and Decoder 

 
The recommended CCSDS 131.2-B-1 standard introduces a Serial Concatenated Convolutional Code (SCCC). Main goal of this code is to allow an efficient use of available bandwidth, by allowing to select from 27 valid configurations with a wide range of constellations, block lengths and code rates.

The outstanding error correction performance of the SCCC code in combination with the high data rates makes this IP core the ideal fit for further applications where high throughput and high spectral efficiency is key for operation.


PRODUCT BRIEF  


FLEXIBILITY


LATENCY


THROUGHPUT


ERROR CORRECTION


Applications
​ 


  • Satellite communication
    • High data rate telemetry applications
    • Earth Exploration Satellite Service (EESS)
  • Applications with the highest demands on forward error correction
  • Applications with the need for a wide range of code rates and block lengths

Standard Features the Core Supports


  • Compliant with CCSDS 131.2-B-1
  • Support for all 27 ACM formats
  • Support for all modulation schemes (QPSK, 8-PSK, 16-APSK, 32-APSK, 64-APSK)


      

   Your Benefits


      

  • Burst-to-burst on-the-fly configuration
  • High payload block length granularity (between 5,758 and 43,678 bits)
  • High code rate granularity (code rates between 0.36 and 0.90)
  • Configurable amount of turbo decoding iterations for trading off throughput and error correction performance
  • Low-power and low-complexity design​
  • Available for ASIC and FPGAs (AMD Xilinx, Intel, Microchip)
  • Deliverable includes VHDL source code or synthesized netlist, VHDL testbench, and bit-accurate Matlab, C or C++ simulation model



Learn more about

CCSDS
Standard
 

  Creonic Turbo
Encoder / Decoder 
IP Cores

 

We are 
ISO 9001:2015
certified


Our customers can rely on consistently high quality, guaranteed by our certified quality management. 


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