OpenROADM oFEC (Open Forward Error Correction) is a core element of the OpenROADM initiative, providing a standardized, open-source FEC solution for high-speed coherent optical networks.
Creonic’s oFEC IP cores deliver high coding gain through a fully parallel, pipelined decoder architecture with 3 soft-decision (SD) and 2 hard-decision (HD) decoding steps. It supports data rates from 200G to 800G, including Probabilistic Constellation Shaping (PCS) modes to enhance spectral efficiency, noise tolerance, and transmission reach. In addition to the FEC engine, the solution includes an interleaver/deinterleaver and parallel CRC checks for final payload validation. An FPGA version operating at 10 Gbps is available for prototyping, testing, and lower-bandwidth use cases.
Optimized for low latency, energy efficiency, and seamless integration, the oFEC core enables reliable high-speed transmission for hyperscale data centers, telecom infrastructure, and high-performance computing.
Interested? Contact us!
Kevin Christoffers
Director - Business Development & Sales
Product Brief
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- High-speed coherent optical communication up to 800G
- Long-haul and metro optical transport
- Multi-vendor interoperability
- OpenZR+ and pluggable coherent optics
- Compliant with “Open ROADM MSA
- 6.0 W B400G Port Digital
- Specification (400G-800G)”.
- • Compliant with “OpenZR+
- 200G/400G/600G/800G”.with “Open ROADM MSA
- 6.0 W B400G Port Digital
- Specification (400G-800G)”.
- • Compliant with “OpenZR+
- 200G/400G/600G/800G”.
We are ISO 9001:2015 certified
Our customers can rely on consistently high quality, guaranteed by our certified quality management.
- Support all modes in OpenROADM 6.0 and OpenZR+
- Support Probabilistic Constellation Shaping (PCS)
- Support QPSK, 8-PSK, 16-QAM, and 16-QAM PCS
- Payload throughput of 200G/400G/600G/800G on ASIC
- Payload throughput of 10Gbps on FPGA
- Low-power and low-complexity design
- Deliverable includes VHDL source code or synthesized netlist, VHDL testbench, and bit-accurate or floating point Matlab, C or C++ simulation model
- Available for ASIC and FPGAs (Intel/Altera, AMD / Xilinx)
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